Fully Scalable Power-Efficient Electronic Digitizer Architecture Navy SBIR FY2012.1 Sol No.: Navy SBIR FY2012.1 Topic No.: N121-093 Topic Title: Fully Scalable Power-Efficient Electronic Digitizer Architecture Proposal No.: N121-093-1101 Firm: Photonic Systems, Inc. 900 Middlesex Turnpike Building #5 Billerica, Massachusetts 01821 Contact: Gary Betts Phone: (760) 839-8211 Web Site: www.photonicsinc.com Abstract: Photonic Systems, Inc. (PSI) and GMR Research & Technology (GMR) propose a novel combination of electronic and photonic hardware together with digital processing software that implements an ultra-wideband, power-efficient, high-performance analog-to-digital converter (ADC). This unique combination of hardware and software enables a wide ADC design trade space. Consequently this approach makes the design point specified in the solicitation attainable by the end of Phase II of this SBIR program, and can easily be adapted to the design of other ADCs at different points in the ENOB vs. sampling rate trade space. The PSI/GMR team's innovative design meets this program's challenging ENOB, dc power, and sampling rate goals by leveraging the best features of the team members' work on previous ADC programs: sampling with wide-bandwidth photonics, interleaving of multi-channel ADCs, and processing algorithms that compensate for channel mismatch, timing skews, etc., and thus enable high dynamic range with minimum power consumption. The result is an ADC system whose design permits maximum use of COTS technology, thereby achieving extraordinary performance using ordinary components. The approach is scalable in ENOB and sample rate as the performance of electronic ADCs improves, and its output is compatible with standard interfaces for digital data signal transfer. Benefits: The PSI/GMR team possesses more than 25 years experience in the design of advanced analog-to-digital converters (ADC) and has set several records for performance, one of which still holds today. To the program proposed here, the PSI/GMR team has applied the following four "lessons learned" on earlier government-sponsored R&D programs to yield key benefits: 1. Keep the architecture simple. The ADC architecture that PSI/GMR proposes combines the individual strengths of three approaches that were developed on each of three earlier programs. By applying each approach to the part of the ADC design where it is most beneficial, PSI/GMR has achieved an overall design that is simpler than any of the previous designs. 2. Recognize the limits of the various technologies. This lesson is in some sense the complement to lesson #1 -- i.e., recognize not only the strengths of a technology or algorithm but also its limitations. For example, signal processing can do some incredible things, but there are also compensations that are challenging even for the most advanced signal processing algorithm. Too often in the past the design attitude has been, "we will fix it with signal processing." And while in principle this may be a valid strategy, the resulting algorithm often turns out to be so complex that it is either too slow or too expensive (or both). 3. Make maximum use of COTS components. Another key benefit of the PSI/GMR team's ADC architecture is that it uses an innovative design to extract extraordinary performance from ordinary components. The result is a high-performance ADC that is cost-competitive to produce. 4. Leave signal processing to the experts. A key benefit of the proposed effort is that its signal processing portion will leverage algorithms specifically designed to deal with ADC issues -- such as compensation for channel mismatch and nonlinearity -- that were developed by signal processing experts now at GMR. On earlier programs, the team now at PSI did not have the benefit of personnel with signal processing experience. Return