Rise Tool for Updating Legacy Code to Multi-thread, Multi-core Processor Systems Navy SBIR FY2013.2 Sol No.: Navy SBIR FY2013.2 Topic No.: N132-099 Topic Title: Rise Tool for Updating Legacy Code to Multi-thread, Multi-core Processor Systems Proposal No.: N132-099-0346 Firm: Harmonia Holdings Group 2020 Kraft Drive, Suite 1000 Blacksburg, Virginia 24060-6491 Contact: Marc Abrams Phone: (540) 951-5901 Web Site: www.harmonia.com Abstract: Central Processing Unit (CPU) chip makers made two advancements in recent years: (1) hyper-threading (e.g., Intel HT technology) to allow a single processor core to execute multiple instructions simultaneously, and (2) fabrication of dies with multiple processor cores. Exploiting those requires new code in C#, Java, or other languages that embrace threads. A thread is a conventional sequential program, but threads can be scheduled to execute in parallel. A key challenge is that two threads must serialize their work on shared memory areas or data structures (or else one could destroy the data of the other thread), requiring special synchronization primitives (e.g., monitors, message passing). This is a non-trivial job for a programming team. Rise Multi-Core fills the need is for automated analysis that can improve older sequential code to make use of multiple cores. The Desired Future State is a tool to analyze existing legacy code and apply transformations it to effectively use threading and multi-cores to improve performance (e.g., lower time for route planning, or increased throughput for graphical operations). Benefits: A recent survey made by Intel and developer web site Slashdot found that only 17% of responding developers classified themselves as experts on using multi-core processors, and almost half (44%) had little or no hands-on experience with multi-core programming. Therefore the knowledge based does not widely exist to make new code efficient on multi-core processors, much less legacy code. Rise Mulit-Core will extend the lifetime of an investment made for years in software that executes one operation at a time ("single-threaded," except for event handlers). The anticipated result is an alternative and novel method of automating the parallelization of legacy software for multi-core processors using cyclical performance tuning driven by machine learning. The result will break new ground from a science and technology side in that existing parallelization tools rely solely on code analysis (which we also include), whereas we go further by applying machine learning to create a system that automatically adjusts performance through the lifecycle of a system, which can extend to a decade or more in DOD. Return