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Coherent Clocking in Digital Arrays
Navy SBIR 2006.2 - Topic N06-164 ONR - Ms. Cathy Nodgaard - [email protected] Opens: June 14, 2006 - Closes: July 14, 2006 N06-164 TITLE: Coherent Clocking in Digital Arrays TECHNOLOGY AREAS: Information Systems, Sensors, Electronics, Battlespace ACQUISITION PROGRAM: Frequency Antennas & Topside Program Manager, code PMW 180-D4/E2 OBJECTIVE: Establish viable procedures for insuring that clock distribution errors do not contribute to effective clock jitter in digitally beam formed sensor arrays serviced by either single or multiple clocks. DESCRIPTION: The virtues of active arrays, steered in the digital domain by true time delay, are increasingly accepted. However, there are problematic aspects of clocking, especially in case of element level digitization using distributed clocks. A familiar one is the issue of compensating for differences in data transmission time from the elements to the beam former. The one of interest here is the necessity for the sampling to occur at the same time at every element -- otherwise the errors act as effective clock jitter, degrading the limiting signal to noise ratio of the array. Were a high quality master clock at the full sampling rate Cs distributed to all the elements, the periodic nature of the clock means the maximum error in the sample time would be 1/Cs. But this solution is often viewed as too cumbersome and expensive to implement. Frequently individual Cs rate clocks are placed at every element and slaved to a lower rate master clock Cs'. This keeps them synchronized in the sense of having the same number of samples over intervals of many sample periods, a clear requirement. However, their short term errors -- cycle to cycle fluctuations and drift of average rate -- will still be independent and contribute to the effective aperture jitter. Decimating or otherwise temporally averaging high sample rate data from individual elements and spatially averaging data may decrease this jitter in a statistical sense. An experimentally validated study of the optimal method of clocking a distributed array is desirable. PHASE I: Define an optimal scheme for clocking a spatially distributed, m element digital array designed to sample signals with 500 MHz information band width. Mathematically investigate the impact of several clocking schemes as a function of the inherent jitter distribution of potential clocks. Determine the differential cost per element of each choice including an estimate of distributing the master clock, if any, and determine what method produces the smallest aperture jitter. PHASE II: Construct a 2 element demonstrator of this clocking theory and demonstrate the validity of conclusions drawn in phase 1. It is essential that the quantization noise of the ADC triggered by this clocking scheme not be dominated by sampling clock jitter. Aggregate aperture jitter below 100 fs is desired. PHASE III: Integrate the optimized clocking scheme in a digital beam forming effort. PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: Active arrays are becoming widely popular as a way of realizing directional antennas. Thus this topic is relevant to the commercial communications world, especially the wireless one. REFERENCES: 2) www.mwrf.com/articles/articleID/11069/11069.html 3) www.analog.com/0,2890,3%255F%255F,46659,00.html 4) For small arrays, F. L. Walls, "PM and AM Noise of Combined Signal Sources," Proc. of 2003 Frequency Control Symposium and 17 European Frequency & Time Forum, Tampa, FL, May 4-8, 2003. For widely separated clocks or clock using sites, see S. Francis, B. Ramsey, S. Stein, J. Leitner, M. Moreau, R. Burns, R.A. Nelson, T.R. Bartholomew, and A. Gifford "Timekeeping and time dissemination in a distributed space-based clock ensemble," Proc. 2002 Precise Time & Time Interval Mtg., Reston, VA, pp 201-214, Dec., 2002. KEYWORDS: digital beam forming, clock jitter, clock synchronization, clock screw, distributed arrays, aperture jitter TPOC: Deborah Vechten
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