TECHNOLOGY AREAS: Information Systems, Sensors, Weapons

ACQUISITION PROGRAM: DASH FNC; PMA-280, Tomahawk Weapons System

OBJECTIVE: Develop a tool with a graphical user interface (GUI) that can be used to translate an algorithm designer�s work directly into optimized firmware code.

DESCRIPTION: As guidance algorithms become more complex, the common view is that more general-purpose resources (microprocessors, memory, and digital signal processors) are required to support them. This is inefficient both from a hardware and programming perspective. The intent of this topic is to circumvent the use of these general-purpose components through the direct implementation of as much of an algorithm as possible onto one or more FPGAs. The two major savings that could be gained are in development time and resources as well as resources required on the target item. Although the development resources that could be saved would primarily be software and firmware programmer time, hardware design time would also be reduced since some of the hardware would be standardized to accept the tool�s output. The target item resources that would be saved are thermal load capacity, since the FPGA would put off less heat than a comparable processor/digital signal processor (DSP) chip combination, volume, since putting in one or even two FPGAs in place of a processor/DSP combination would save overall space, and power load capacity, since the FPGAs would require somewhat less power than the processor/DSP chip combination.

The software tool should enable the efficient implementation of signal processing algorithms directly onto an FPGA, allowing rapid development, testing and integration of algorithms on hardware that is identical to that which will be used in the final system. The tool design should also provide optimal processing capacity on existing and future FPGAs. The current development process requires a significant amount of sequential efforts by various technical groups to arrive at functional hardware. To shorten development time and improve performance of the resultant system, the most often used image processing functions (such as the Fast Fourier Transform (FFT) and edge detect) should be precompiled and optimized for the target platform. The software tool that is being requested is not simply a set of image processing intellectual property cores, nor is it intended to replace firmware programming altogether with a higher level language or a layout tool. The effort is intended to give software and algorithm engineers a framework that provides an efficient method to use existing algorithms and easily extend algorithms that can be used as building blocks to either augment or replace microprocessors and/or DSP chips. It is intended to help keep/simplify hardware in the loop, and as such should target several commonly used image processing functions on a given platform. The tool must be general enough to support FPGAs from common vendors (Altera and Xilinx, for example) and it should provide for adding capability (i.e., additional functions and additional platforms) as may be reasonably expected in support of future requirements. The tools must be easily used by competent professionals and provide cross-platform functionality.

The reason general-purpose processors are still used for implementing algorithms is that it allows them to be changed, even through the testing and evaluation period of the weapon�s life. It is the hope that this level of flexibility is maintained while the advantages of direct firmware implementation are taken advantage of. This is non-trivial because not only are there a wide variety of algorithms, but there are also many different FPGAs, and not all are directly compatible. Making a tool like this function for many algorithms as well as making it able to program/use many FPGAs from varying companies will be a formidable challenge.

PHASE I: Determine the feasibility of the proposed programming tool by designing and demonstrating the basic functionality of a rudimentary but representative group of algorithm components that can be implemented on one FPGA platform.

PHASE II: Develop and demonstrate a prototype a tool to allow implementation of more general algorithms on multiple FPGA platforms and provide an appropriate user interface.

PHASE III: Demonstrate and transition the complex algorithm implementation and operability with multiple FPGA platforms.

PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: The availability of this tool could prove very useful in the commercial sector as it would provide for reduced development costs, and making hardware implementations more attractive. The technology would be critical for portable or concealable electronic devices and useful in applications requiring minimizing volume, power and thermal factors.

REFERENCES:
1. Ye, A. & Rose, J. (2006). Measuring and utilising the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks. IEE Computer & Digital Techniques Journal, Vol.153, No.3, pp.146-156

2. Kundarewichm, P. and Rose, J. (2004). Synthetic Circuit Generation Using Clustering and Iteration. IEEE Trans. on Computer-Aided Design, Vol. 23, No. 6, pp. 869-887

3. Cong, J., Fan, Y., Han, G. & Zhang, Z. (2004). Application-Specific Instruction Generation for Configurable Processor Architectures. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays

4. Advanced FPGA Design: Architecture, Implementation, and Optimization. Steve Kilts, Wiley-IEEE Press 2007

KEYWORDS: Field Programmable Gate Array (FPGA); Processing; Embedded; Algorithms; Fast Fourier Transform (FFT); Programming

** TOPIC AUTHOR (TPOC) **

DoD Notice:   Between November 10 and December 12, 2010, you may talk directly with the Topic Authors to ask technical questions about the topics. Their contact information is listed above. For reasons of competitive fairness, direct communication between proposers and topic authors is not allowed starting December 13, 2011, when DoD begins accepting proposals for this solicitation.

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