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Multi-fovea Parallel Sensor-processor Architectures and Algorithms to Improve UAV Based Recognition, and UAV Sense and Avoid capabilities
Navy SBIR 2011.1 - Topic N111-063 ONR - Mrs. Tracy Frost - [email protected] Opens: December 13, 2010 - Closes: January 12, 2011 N111-063 TITLE: Multi-fovea Parallel Sensor-processor Architectures and Algorithms to Improve UAV Based Recognition, and UAV Sense and Avoid capabilities TECHNOLOGY AREAS: Sensors, Electronics OBJECTIVE: Develop high-resolution (~ 1MPix), high-speed (~ 1000 fps for selected image regions) multi-fovea parallel sensor-processor architectures and the associated image processing algorithms for robust, high-performance terrain analysis, object signature recognition, and Sense and Avoid (SAA) . DESCRIPTION: There is an increasing need to perform higher levels of sensor signal processing on board UAVs to relieve the requirements for transmitting Full Motion Video (FMV) over already overloaded data links to the ground station for processing. The goal for this effort is to introduce this capability onto UAV platforms with minimal impact on SWaP (size, weight, and power), for applications like persistent surveillance, and sense and avoid. Under persistent surveillance the improved processing capability would involve techniques for locating and identifying targets of interest in complex backgrounds. The Sense and Avoid (SAA) application would require searching large areas( minimal forward hemisphere) for airborne objects using motion clues from frame subtraction. Once the airborne objects are located they must be tracked to determine collision potential and generate escape routes. Smart sensors with on-chip processing capability will be able to address this challenge if the object signatures can be detected and identified within unprecedented response time (typically below 1 msec for 1kHz imagers)). However, this specification can only be met with complex algorithms critically optimized for novel massively parallel sensor-processor architectures. Previous efforts already demonstrated that increasing the near-sensor ("focal plane") computational capability could only be traded against sensor resolution. Thus, designing high resolution, tightly integrated sensor-processor arrays (VIS/NIR focal plane array) is still in its infancy, and will require more development to provide significant on-chip processing capability. A possible evasion is to use a combination of high resolution sensor arrays with relatively simple nearest neighbor processing incorporated in the readout integrated circuits (ROICs) combined with a subsequent chain of "fovea processors" (a multi-chip approach). These multi-fovea architectures could support complex signature analysis around selected spatial locations at high frame rates thereby significantly increasing the probability of correct target identification by utilizing the spatial resolution needed for analyzing fine details in selected foveal areas. If properly designed, multi-fovea / multi-core processors will also show an improved robustness in extreme environmental conditions (due to dynamically maskable pixel level and exchangeable foveal processing nodes). The effort should rely on state-of-the-art commercial of-the-shelf multi-fovea ROIC solutions with simple nearest neighbor processing (1/4 MPix solutions with multi-scale processing and frame differencing capability are already available today for customization) and focus on the complementary massively parallel multi-fovea processing architecture design and implementation with the associated embedded software solutions. PHASE I: Complete a feasibility study on massively parallel, multi-fovea sensor-processor chip architectures and algorithms for high-performance terrain analysis, object signature recognition, collision guidance and avoidance. Demonstrate the feasible architectures with the associated algorithmic solutions. PHASE II: Design, develop and fabricate a massively parallel, multi-fovea sensor-processor chip-set with the associated algorithms for high-performance terrain analysis, object signature recognition, collision guidance and avoidance. Demonstrate the functionality of the integrated multi-chip device. PHASE III: Develop and execute a plan to manufacture the sensor-processor(s) developed in phase II, and assist the NAVY in transitioning this technology to the appropriate prime contractor(s) for the engineering integration and testing of the proposed advanced sensor-processors. PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: Maritime & aviation collision avoidance sensors and medical uses. REFERENCES: [2] Rekeczky, C., I. Szatmari, D. Balya, G. Timar, and A. Zarandy, "Cellular multiadaptive analogic architecture: a computational framework for UAV applications", Circuits and Systems I: Regular Papers, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, pp. 864�884. doi:10.1109/TCSI.2004.827629, 2004. [3] A. Richards, J. Bellingham, M. Tillerson, and J. How, "Coordination and Control of Multiple UAVs", AIAA Guidance, Navigation, and Control Conference and Exhibit, AIAA 2002-4588, Monterey, California, 2002. KEYWORDS: Sensor-processor architecture, Near-pixel processing, IR detector, Electro-optical detector, Sense and Avoid, Terrain recognition, Object signature analysis.
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