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High-Speed, High-Fidelity, Reprogrammable Kernel for Use in Digital Radio Frequency Memory (DRFM) Systems and High-Speed Signal Digitization and Processing Applications
Navy SBIR 2012.1 - Topic N121-034 NAVAIR - Ms. Donna Moore - [email protected] Opens: December 12, 2011 - Closes: January 11, 2012 N121-034 TITLE: High-Speed, High-Fidelity, Reprogrammable Kernel for Use in Digital Radio Frequency Memory (DRFM) Systems and High-Speed Signal Digitization and Processing Applications TECHNOLOGY AREAS: Sensors, Electronics OBJECTIVE: Evaluate, design, fabricate, and demonstrate the framework of a high-speed, high-fidelity, reprogrammable kernel for use in digital radio frequency memory (DRFM) systems and high-speed signal digitization and processing applications. DESCRIPTION: The advent of modern electronics is enhancing our ability to save warfighters� lives. However, the enemy�s capabilities are also improving significantly. Therefore, it is imperative that our fighting men and women are equipped with only the best and most up-to-date equipment possible. Doing so is facilitated by the decreasing cost of electronics over the last decade, a fact that will enable us to deliver more cost-effective solutions. With modern electronics, items such as a DRFM, which is an electronic method for digitally capturing and retransmitting a radio frequency (RF) signal in radar jamming, can be rendered more difficult to detect. Two reasons are the higher number of bits and higher sampling speeds of state-of-the-art analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). For example, the higher number of bits in ADCs and DACs allows for a higher spurious-free dynamic range (SFDR), thus making it more difficult for a radar system to detect when a DRFM is being used. Higher sampling speed affords a higher intermediate frequency (IF) bandwidth, thereby making it possible to use much simpler and less expensive RF front ends, as well as allowing for lower latency and increased resolution. The kernel, which is the core part of the DFRM�s operating system, takes an analog IF input and digitizes it with an ADC, processes the data in one of several ways within a field-programmable gate array (FPGA) chip, and outputs the altered digital data through a DAC. Having a high-speed, high-fidelity, reprogrammable kernel will result in significant improvements in the Navy�s ability to defeat cutting-edge radar systems. While the focus of this SBIR effort is on DRFM systems, the product developed should be a modular kernel design that can be used for many applications, not solely for a DRFM. Therein, the FPGA chip should allow the hardware to be reconfigured in numerous ways for air, land, and sea applications. Furthermore, the firmware should have the basic functions needed to implement a DRFM, as well as allow additional features to be added by the end user. In fact, the hope is that the hardware incorporating the proposed kernel can be used for any project requiring high-speed data conversion and signal processing. To defeat modern radar systems, the design must meet the following minimum specifications. The system must have a total SFDR of greater than 60 decibels (dB), the kernel section's total latency must be less than 60 nanoseconds, and the system must have four digital channels and be able to generate delays in excess of 64 microseconds. Other goals include the ability to send portions of the data stream to a PC for analysis, to control the device via PC, and to easily reconfigure the firmware. The system must be clocked at a minimum of 1 gigahertz (GHz). Finally, the system should be able to provide frequency modulation with 0.1-hertz (Hz) or smaller steps on time-delayed signals. PHASE I: Determine the feasibility of designing a system meeting the specifications stated in the "Description" section for both hardware and firmware solutions. Develop an approach for executing all aspects of the design, including frequency modulation, time shift, and hardware. Conduct modeling of the firmware solutions for the targeted device to prove the concept�s ability to satisfy the stated requirements. PHASE II: Develop a hardware, firmware, and user interface as a prototype. Demonstrate and validate that the prototype meets the required specifications and is manufacturable. PHASE III: Test the system and integrate it into military applications. PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: The kernel portion devised under this SBIR project can be used for any weapon system that requires high-speed analog data capture, processing, and transmission. Because of the reconfigurable firmware, the device can be repurposed for many applications, including, but not limited to, hardware-in-the-loop systems requiring high bandwidth and high signal fidelity, radar test and evaluation, and analog control systems. REFERENCES: 2. Cloninger, C. Data converter function can help solve cost and size design challenges in 3G and 4G wireless infrastructure. Retrieved on 26 May 2011 from http://www.analog.com/library/analogdialogue/archives/41-10/adcs_for_wireless.html 3. Wang, Z., Gao, M., Li, Y., Jiang, H., & Ying, S. (2008). The hardware platform design for DRFM system. In Signal processing, 2008. ICSP 2008, 9th International Conference on, October 26-29, (pp. 426-430). doi: 10.1109/ICOSP.2008.4697162 KEYWORDS: Digital Radio Frequency Memory (DRFM), Reconfigurable, High Speed, Kernel, Digital-to-Analog Converter (DAC), Analog-to-Digital Converter (ADC)
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