N121-084 TITLE: Processing of Large Wide Area Airborne Sensor (WAAS) Data Streams in Hardware

TECHNOLOGY AREAS: Air Platform, Information Systems, Sensors

ACQUISITION PROGRAM: Persistent and Surgical Persistent Surveillance (FY12 new start)

OBJECTIVE: Develop and demonstrate a set of exploitation algorithms that can operate in real-time power-efficient hardware against gigabit-per-second data streams with performance equivalent to existing server-based applications.

DESCRIPTION: Day/night WAAS payloads for tactical unmanned aircraft system (UAS) platforms in development can generate gigabytes to terabytes of data-per-hour. Operational requirements exist for these payloads to generate and disseminate actionable intelligence from the platform. When matured, this capability can be integrated into any of the current WAAS programs including the ONR developed Wide Focal Plane Array Camera (WFPAC) sensor that will begin an operational deployment in fiscal year 2012. On-board processing tasks to be considered by this topic include the detection of watchbox and tripwire violations, cued tracking of movers responsible for the generation of an alert, and, if possible, full-scene tracking of movers.

Trackers and software to detect specific alert conditions have been developed and demonstrated to keep up with 7 gigabit-per-second WAAS data streams and are rapidly maturing. These wide area trackers run in software on power-intensive high-end servers which are not suitable for tactical on-board processing environments. Innovation is needed in order to enable trackers and behavior recognition algorithms that currently run in software on large distributed servers to run in real-time in firmware. Proposers should consider leveraging state-of-the-art field programmable gate arrays (FPGAs) that have the ability to handle gigabytes-per-second streams and state-of-the-art multi-core digital signal processors (DSP) that have the processing power of much larger servers. This hardware environment should be exploited in order to meet the transition program requirement for a processing board that weighs only a few pounds and consumes less than 50 watts. Successful proposers will also consider how to incorporate the filters ground track processors use to prevent spurious detections from being included in a track or declared an alert condition. These spurious detections often result from dead pixels or from in-scene contrast variations. Matured on-board exploitation will achieve 90% true alert detections (e.g. trip wire violation) with only 10% false alerts and will fuse tracklets as needed to produce tracks consisting of at least 80% of the ground truth track. Challenges of this topic include: 1) processing very large data streams in real-time, 2) hosting trackers and behavior recognition algorithms in firmware, 3) meeting size, weight and power goals, and 4) achieving acceptable tracking/alerting performance.

PHASE I: Develop and mature a technical approach towards on-board processing of data from very large focal plane arrays in power and weight restricted hardware. Identify key technical risks, develop risk mitigation and track progress on key technical parameters. Select or develop exploitation software and model its performance in flight-suitable hardware (FPGAs/DSPs) simulators paying careful attention to performance.

PHASE II: Port promising exploitation software to hardware and demonstrate acceptable performance. The prototype should meet size and power requirements while achieving high accuracy alerts and tracks with a high completeness.

PHASE III: Transition the developed product to a specific tactical wide area sensor program.

PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: The commercial market for this technology includes border security and law enforcement. The detection of persons moving across a border is only actionable if detected in real time. Bandwidth availability generally prevents gigabyte-per-second data links from being operated over long distances.

REFERENCES:
1. Representative Specification for a Field Programmable Gate Array, Xilinx Field Programmable Gate Arrays, http://en.wikipedia.org/wiki/Xilinx.

2. Representative Specification for an Advanced Digital Signal Processor, http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=dsp&familyId=132�ionId=2&tabId=57.

3. Aviation Week; 2/4/11; "Shadow Punches Above its Weight" (background on the WFPAC program)

4. Relevant platform specifications for the Shadow UAS, http://www.aaicorp.com/products/uas/shadow_family.html.

KEYWORDS: On-board processing; video exploitation; wide area sensors; exploitation; firmware; digital signal processors; field gate programmable arrays

** TOPIC AUTHOR (TPOC) **

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