Large Time Band Width Product Signal Acquisition Processors
Navy SBIR 2014.1 - Topic N141-065
ONR - Ms. Lore Anne Ponirakis - email@example.com
Opens: Dec 20, 2013 - Closes: Jan 22, 2014
N141-065 TITLE: Large Time Band Width Product Signal Acquisition Processors
TECHNOLOGY AREAS: Information Systems, Sensors, Electronics
RESTRICTION ON PERFORMANCE BY FOREIGN CITIZENS (i.e., those holding non-U.S. Passports): This topic is "ITAR Restricted". The information and materials provided pursuant to or resulting from this topic are restricted under the International Traffic in Arms Regulations (ITAR), 22 CFR Parts 120 - 130, which control the export of defense-related material and services, including the export of sensitive technical data. Foreign Citizens may perform work under an award resulting from this topic only if they hold the "Permanent Resident Card", or are designated as "Protected Individuals" as defined by 8 U.S.C. 1324b(a)(3). If a proposal for this topic contains participation by a foreign citizen who is not in one of the above two categories, the proposal will be rejected.
OBJECTIVE: Develop a dynamically reconfigurable, minimal latency and power Digital Signal Processing (DSP) hardware base to simultaneously handle 100ís of diverse, possibly overlapping signals for multi-functional situational awareness.
DESCRIPTION: A new Digital Signal Processing (DSP) subsystem is needed that allows optimized, multi-threaded signal classification in as near real-time as possible. At a minimal, the subsystem should operate on a stream (from a first-in first-out memory buffer) of a single wideband representation of 500 MHz+ of spectrum. Signals within this spectrum will contain a mix of known and well-behaved signals as well as unknown signals with unknown behaviors or properties. The subsystem should handle numerous simultaneous signals (at least 30 with a goal of 100+) and be able of classify signals that shift their center frequency unpredictably, lie wholly or partially on top of other signals, have inherently low signal to noise ratios, or use non-commercial standard waveforms. The DSP threads should track known signals, classify unknown signals, or do a exhaustive search of a specific time/frequency swath to identify new or unknown signals for further classification or tracking. The ideal system should be composed of commercially available parts such as field-programmable gate arrays (FPGA), digital signal processors (DSP), graphical processing units (GPUs), and general processing processors (GPP) or hybrids thereof with a shared-memory architecture for extremely fast multi-thread processing of wideband signal data. The ultimate metrics quantify the wall-plug energy and time expended per signal per GHz of spectrum handled by a single chain. The system should be programmable with common languages to minimize re-transcription of DSP software.
PHASE I: Define and develop a concept for a Large Time Band Width Product Signal Acquisition Processor that can meet the performance constraints listed in the description. Perform modeling and simulation to provide initial assessment of concept performance and SWAP. Phase I Option, if awarded, would include the initial layout and capabilities description to build the unit in Phase II.
PHASE II: Development of prototype based on Phase I work for demonstration and validation. The prototype should be delivered at the end of Phase II, ready to be tested by the government.
PHASE III: Integrate the Phase II developed Large Time Band Width Product Signal Acquisition Processor prototype within the FNT-FY15-04 SIRFSUP architecture for transition to BLQ-10 Improvement Program.
PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: Spectrum Survey, Adaptive Commercial Communications
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KEYWORDS: Digital Signal Processing (DSP); High bandwidth Processing; Hybrid DSP Architectures; Signal Classification; Signal Detection; Spectral Awareness