Scalable Aircraft Hardware Open System Technologies (HOST) Prototype Development
Navy SBIR 2016.2 - Topic N162-089
NAVAIR - Ms. Donna Attick -
Opens: May 23, 2016 - Closes: June 22, 2016

TITLE: Scalable Aircraft Hardware Open System Technologies (HOST) Prototype Development

TECHNOLOGY AREA(S): Air Platform, Electronics, Information Systems

ACQUISITION PROGRAM: Joint Strike Fighter F-35 Lightning II Program

OBJECTIVE: Develop, demonstrate and validate scalable hardware based on the design and interface requirements in the Tier 1 [1] and Tier 2 [2] Hardware Open System Technologies (HOST) standards capable of hosting traditionally developed software, as well as software designed/developed in accordance with more current openly available standards (e.g. Future Airborne Capability Environment (FACE) [3]).

DESCRIPTION: Today’s military aviation airborne systems are typically developed for a unique set of requirements and managed by a single vendor utilizing proprietary interfaces. This stovepipe type of development process has served the military aviation community well in the past. However, it comes with some undesired side effects resulting from the fact that proprietary interfaces were used versus current state-of-of-the-art interfaces such as VITA standards for embedded hardware and the Ethernet standard for networking. Potential negative impacts of this closed interface approach include long lead times, cumbersome upgrade processes, and the lack of cross aircraft platform hardware/software compatibility which result in platform-unique designs. Ultimately, these proprietary interfaces force any change, even an obsolescence redesign to require a laborious effort (repeated for every change on every platform) to reanalyze these custom interfaces which only the system designer / integrator knows (and potentially slowly forgets the undocumented details over time) and verify that they are again implemented properly (potentially requiring reverse engineering). To counter this trend, the Hardware Open System Technologies (HOST) standard was developed. HOST is an open, high performance, cost effective, and truly sustainable embedded system architecture engineered with well-defined interfaces based on established industry standards (like VITA and Ethernet) at the component or HOST Module level, so that scalability and compatibility across the breadth of military platforms (e.g. aircraft, ground vehicles), systems (e.g. mission computers, displaces, radars, radios), and applications (e.g. mission, sensor, and image processing) can be achieved. This will also enable affordable integration of new technology based on the ease to integrate to a known interface (e.g. known / VITA backplane connections).

The HOST architecture provides the framework for developing embedded computing systems for U.S. military platforms. HOST compliant hardware, based on the referenced standards [1, 2, 3, 5, 6, 7], will change the paradigm of traditional hardware acquisition in much the same way that release of the IBM PC interface specifications in the 80‘s created the PC market and open architecture software standards have changed the portability of software (e.g. apps). HOST is anticipated to leverage capabilities of hardware only now being introduced to the embedded system market. It is also expected to create an infrastructure on which new software architectures (e.g. FACE) can be created. And when all of the benefits of FACE and HOST are eventually realized in conjunction with each other, embedded system application software will become portable and agnostic of the hardware on which it runs. For example, a processor upgrade funded by one activity (or a vendor interested in marketing upgraded performance in a backward compatible format) can be leveraged by any other activity within the Naval Aviation Enterprise (NAE) that is also based on the HOST Standard using the same Tier 3 specification.

The objective of and first priority (1) for this topic is to develop innovative prototype hardware (e.g. HOST module) capable of fulfilling the HOST interface requirements utilizing the smallest size (i.e. real estate on a VMEbus International Trade Association VITA 48.2 6U circuit card; e.g. <5% of the board real estate), lowest power (i.e. electrical power consumption, <1 watt / heat generation), smallest weight and satisfying the harsh military aerospace environmental requirements (e.g. 85 degree C maximum temperature). The prototype may either be in the 6U or 3U format (i.e. HOST Tier 2), which constrains the module in three dimensions (i.e. 233.35x100 mm 6U and 100x160 mm 3U with a =1 inch slot pitch for both). The second priority (2) for this topic is to provide the maximum flexibility in the means by which the HOST required interface is implemented. For example a design to include developing an innovative way to fulfill a particular Tier 2 requirement that allows the same hardware to fulfill two or more logical interface requirements over the same physical interface (e.g. switchable firmware setup interface protocol). The third priority (3) is to provide the most innovative capability to the proposed HOST module, again with the lowest space, weight and power (SWaP). Simple examples (in decreasing levels of complexity and likely innovation) include creation of a secure network server, a Single Board Computer (SBC), or VITA switch card. The fourth and final priority (4) is to fulfill HOST’s overarching objective to show module level interoperability and interchangeability (i.e. the verification the interfaces are adequately defined and implemented by the HOST standard). Teaming across the embedded system market ecosystem to facilitate final transition is encouraged.

PHASE I: Design and determine the technical feasibility of building the most capable prototype hardware innovatively implementing the HOST standardized interfaces. Hardware having general purpose processing (e.g. SBC) should be capable of hosting traditionally developed software as well as software designed/developed in accordance with other open software standards (e.g. FACE). This phase should also include the software capability rehost analysis and design for any proposed general purpose applications (e.g. network server environment).

PHASE II: Develop and demonstrate prototype hardware and capability based on Phase I effort. Validate that the standardized interfaces defined by the HOST Standard (and any additionally proposed capability) have been implemented in the prototype by demonstrating the prototype in a multi HOST module environment. Include a demonstration of the interoperability of the prototype HOST modules on the NAVAIR development test asset which demonstrates interoperability and interchangeability between NAVAIR’s reference system and the prototype developed under this SBIR. The NAVAIR test asset will conform to the HOST 6U OpenVPX Tier 2 standard including slot profile and Ethernet based manager/participant based protocol. The test asset and any necessary support will be made available as government furnished equipment (GFE) as agreed upon by NAVAIR POC and small business.

PHASE III DUAL USE APPLICATIONS: In coordination with a NAVAIR program office, identify a potential hardware system (e.g. secure network server, mission computer, display) for application of the demonstrated capability. Based on program office coordination, design and build hardware, and verify through system testing specific hardware capabilities above and beyond simple interfaces. Private Sector Commercial Potential: NAVAIR currently is developing the HOST standard as an open architecture initiative intended to become the standard upon which embedded systems are specified. The results of this SBIR have the potential to directly feed into future avionics systems being acquired by NAVAIR which will specify use of HOST. Both the Army and Air Force are also participating in HOST’s development with the intent to also require HOST. The HOST standard is also starting to see increased interest from the private sector as the industry realizes the value of establishing an ecosystem of products and market niches for embedded system hardware similar to the current consumer electronics marketplace.


  • Hardware Open Systems Technology – Tier 1 Version 1.0. (Uploaded in SITIS on 4/22/16.)
  • Hardware Open Systems Technology – Tier 2 Version 1.0 (Uploaded in SITIS on 4/22/16.)
  • The Open Group Website. FACE 2.1 Technical Standard;
  • NEXTGEN Avionics Roadmap, Version 2.0;
  • OpenVPX Tutorial.
  • ANSI/VITA 48.2, VPX REDI: Mechanical Specifications for Microcomputers Using Conduction Cooling Applied to VPX
  • ANSI/VITA 65-2010 (R2012), OpenVPX Architectural Framework for VPX
  • For Ref. 2, uploaded file 2 of 2 -- HOST Standard Tier 2 6U v1.0 PAO SOR (2016). (Uploaded in SITIS on 4/22/16.)

KEYWORDS: Interoperability; Avionics; Architecture; Mission Systems; FACE; HOST

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