N233-D10 TITLE: DIRECT TO PHASE II - Time Division Duplex (TDD) Radio Frequency (RF) Beamforming Chip for Active Electronically Scanned Array (AESA)

OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics

OBJECTIVE: Design and demonstrate a Time Division Duplex (TDD) Radio Frequency (RF) beamforming chip that enables the ability to communicate with existing and future Non-Geostationary Orbit (NGSO) satellite constellations using a single Active Electronically Scanned Array (AESA) antenna for both receive and transmit.

DESCRIPTION: PMW 770 is looking to develop a highly integrated semiconductor-based Application-specific Integrated Circuit (ASIC) core TDD RF beamforming chip in order to leverage a single AESA antenna for use with both receive (Rx) and transmit (Tx) for Radio Frequency (RF) communications. The chip is needed to provide the requisite beam steering, polarization tracking, Rx low noise amplification, and Tx power amplification.

The Navy is interested in developing a TDD RF beamforming chip for AESA antennas that meets the following minimum specifications:

• Dual-Polarization antenna element support (Ref 5);
• Half-Duplex architecture to support both Rx and Tx on the same semiconductor beamforming chip;
• Ability to support a single steerable Rx beam (Threshold); ability to support two independently steerable Rx beams and incorporates an integrated power combiner so that the beamforming chip has a single antenna port for the two beams (Objective);
• Operational frequencies:

  - Rx: 10.7 to 12.7 GHz (Threshold), 3 to 40 GHz (Objective);
  - Tx: 14 to 14.5 GHz (Threshold), 3 to 40 GHz (Objective);

• Noise figure of 1.5 dB or better;
• 6-bits of phase control in both Rx and Tx RF signal paths;
• Greater than 25 dB of gain control in both Rx and Tx RF signal paths;
• Ability to support multiple antenna channels per beamforming chip;
• Tx performance requires greater than +16 dBm OP1dB per channel;
• Fast Beam Scan ability (stored beam states);
• A digital Serial Protocol Interface (SPI) to control each beamforming chip; and
• Supports a wide axial ratio circular polarized phased array architecture (example described in US Patent Number: US 11,539,146 B2).

PHASE I: Feasibility documentation MUST NOT be solely based on work performed under prior or ongoing federally funded SBIR/STTR work. Demonstrating proof of feasibility is a requirement for a Direct to Phase II award.

For this Direct to Phase II topic, the Government expects that the small business would have accomplished the following in a Phase I-type effort: conduct a study to determine the technical feasibility and initial design of an affordable TDD RF beamforming chip that enables the ability to communicate with existing and future NGSO satellite constellations using a single AESA antenna for both receive and transmit.

FEASIBILITY DOCUMENTATION: Offerors interested in proposing to this Direct to Phase II topic must include in their response Phase I feasibility documentation that substantiates the scientific and technical merit; proof that Phase I feasibility (described in Phase I above) has been met (i.e., the small business must have performed Phase I-type research and development related to this topic, but feasibility documentation must not be solely based on work performed under prior or ongoing federally funded SBIR/STTR work; and describe the potential commercialization applications. The documentation provided must validate that the proposer has completed goals/results. Work submitted within the feasibility documentation must have been substantially performed by the offeror and/or the principal investigator (PI).

PHASE II: Design, develop, demonstrate, and validate an affordable TDD RF beamforming chip that enables the ability to communicate with existing and future NGSO satellite constellations using a single AESA antenna for both receive and transmit. Develop a comprehensive interface control document that should be made available for both the Department of Defense (DoD) and Defense Contractors. Develop life-cycle support strategies and concepts for the system, per chip cost estimates, and a SBIR Phase III commercialization plan.

PHASE III DUAL USE APPLICATIONS: Refine the prototype and if required, perform additional development to produce a Production Representative Article (PRA). Perform test and validation to certify and qualify components for Navy use. Support the Navy in transitioning the chip for Navy use. Investigate the dual use of the developed technologies for other DoD applications as well as commercial applications to include satellite communication, cellular communication, and other commercial RF-based communication.

REFERENCES:

1. Minimum Viable Product (MVP): https://en.wikipedia.org/wiki/Minimum_viable_product
2. Technology Readiness Levels: https://www.army.mil/e2/c/downloads/404585.pdf
3. Active Electronically Scanned Array: https://en.wikipedia.org/wiki/Active_electronically_scanned_array
4. Time Division Duplex: https://en.wikipedia.org/wiki/Duplex_(telecommunications)
5. S. Das et al., "A Flat-Panel 8�8 Wideband K�/Ka�Band Dual Circularly Polarized Phased Array Antenna for CubeSat Communications," in IEEE Transactions on Antennas and Propagation, 2023: https://ieeexplore.ieee.org/document/10071999/
6. US Patent Number: US 11,539,146 B2: https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/11539146

KEYWORDS: Time Division Duplex (TDD); Low Earth Orbit (LEO); Medium Earth Orbit (MEO); Non-Geostationary Orbit (NGSO); Phased Array; Active Electronically Scanned Array (AESA); Naval Submarine Communications; Super High Frequency (SHF) Communications

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