AN/SLQ-32 IFM/CFR upgrade Navy SBIR FY2004.2 Sol No.: Navy SBIR FY2004.2 Topic No.: N04-165 Topic Title: AN/SLQ-32 IFM/CFR upgrade Proposal No.: N042-165-0 Firm: Welkin Sciences, LLC 102 S. Tejon Street Suite 200 Colorado Springs, Colorado 80903-2200 Contact: J. Reinking Phone: (719) 330-2449 Web Site: www.welkinsciences.com Abstract: We present several methods for upgrading the AN/SLQ-32 IFM/CFR that are applicable to the subject of the solicitation. The methods address measurement of frequency and pulse-width in the presence of digitally modulated CW interference. We also discuss available technology with which to implement digital processors capable of hosting real-time implementations of practical algorithms based on these methods. The hardware design employs a full-mesh serial backplane for card-to-card data transfers and field programmable gate arrays for most of the real-time signal processing. The architecture of a digital processor takes the form of a parallel processing network specifically tailored to match the natural data flow structure of the algorithm it will host. We propose to analyze the various methods in the context of frequency and pulse-width measurement accuracy, and define an appropriate algorithm for an on-ship Navy system. We propose to then design the hardware platform tailored for this algorithm, and define a Phase II demonstration of the upgraded IFM algorithms running in real-time on that hardware platform. Benefits: The anticipated benefits of the Welkin Sciences FPGA design that will be demonstrated in Phase II are threefold: 1) the development of a real-time EW/ES capability that will reduce size/weight/power requirements over traditional solutions while providing a 20-fold increase in compute power per unit volume and a 50-fold increase in inter-card data transfer rates; 2) the development of reusable FPGA firmware libraries for US Navy EW/ES applications; and 3) the development of a reconfigurable hardware platform that may be applied to many applications requiring support for very high input and output data rates. Our company business objectives include significant growth in several areas involving high-end DSP applications. The proposed parallel processor system provides a flexible platform that can host a wide range of systems that process high-speed input data streams, generate high-speed output data streams, perform large-scale computational tasks, or any combination thereof. Our plan is to use this hardware platform on several future R&D efforts primarily for DoD customers, and secondarily for targeted commercial and other government opportunities arising from our commercialization strategy. Return