Application Specific Integrated Circuit (ASIC) Redesign Approach Navy SBIR FY2005.1 Sol No.: Navy SBIR FY2005.1 Topic No.: N05-031 Topic Title: Application Specific Integrated Circuit (ASIC) Redesign Approach Proposal No.: N051-031-0012 Firm: JSI Microelectronics 4235 Forcum Ave. Suite 500 McClellan, California 95652-2101 Contact: Adam Jachniewicz Phone: (916) 648-2089 Web Site: www.jsi-microelectronics.com Abstract: A three stage solution is proposed; 1.Preliminary Analysis, where each part has the die exposed and photographed to identify commonality at the macro level 2.Detailed Analysis,where the macro cell level schematics are developed. This stage also begins with process analysis steps with further photographs of the exposed die. Macro level (block diagram) schematics are constructed from the first pass with more detailed schematics extracted from the macro cells. Packaging options, e.g. combining functional designs on single die, are researched. 3.Design Fabrication, where the macro cells are developed. Timing and electrical models with cell data sheets are created. Once the initial environment is ready a detailed design begins. The macro cells are utilized for simulation and setup, standard cell libraries are utilized for RTL to Synthesis, Place and Route, and Static Timing Analysis. Finally the IC layout is routed followed by verification (DRC, LVS, ERC) and the output to a standard format file (GDSII). This unique method utilizes established commercial technologies and known cost saving approaches. By limiting the number of custom parts the average cost of the replacement part drops dramatically. Benefits: Significant cost savings can be realized by considering the problem as a device family obsolescence issue, rather than a single device. Developing standard libraries from obsolete device families minimizes the cost of reverse engineering parts. These libraries will be easier to match electrical and timing data, which lowers development time and provides a part that is more predictable in behavior. In addition this approach allows:  Standard cell configuration and characterization. With a performance characterization required only once for each standard cell (4 configurations for original manufacturer and 1 configuration for the second manufacturer family  Technology advances which reduces the standard cell size.Parameter controls yield tighter limits. Tighter parameter tolerance controls ensure device performance within acceptable limits.  Utilization of many of the failed devices for the reverse engineering process Out of 10,000 cells only 1 or 2 cells per die are needed. 5 to 10 die ensure proper characterization and parametric tolerances are established.  Standard cell library & common packages. Once a cell library is created and process controls established, turn-around time is reduced to several months versus several years.  Usage of failed devices in photo-imaging facilitates common cell blocks recognition. (Die optimization reduces this capability and increases the difficulty of standard cell definition.)  One system which will utilize 33 OEM devices, 28 of which are packaged in 1 of 3 packages (100 pin, 132 pin, 150 pin QFP).  At least 3 of the 5 are a standard off-the-shelf package configuration.  Buying in larger quantity the unit price per package can potentially be reduced by 30%. Return