Monitoring Reliability of Electronics Via Power-Up Signature Navy SBIR FY2006.1 Sol No.: Navy SBIR FY2006.1 Topic No.: N06-006 Topic Title: Monitoring Reliability of Electronics Via Power-Up Signature Proposal No.: N061-006-0894 Firm: StressTest Genesis Center MSC 3ARP Box 30001 Las Cruces, New Mexico 88003-8001 Contact: Eric MacDonald Phone: (915) 747-6959 Abstract: Reliability problems in contemporary integrated circuits can occur in the field for a variety of reasons: latent defect activation, long-term exposure to radiation, electro migration, etc. Field failures result in incorrect operation during mission critical activities and may lead to loss of life and property. The ability to identify degenerate devices will help to minimize the associated expense of a field failure. Moreover, the ability to detect devices prior to decline will also allow for the timely replacement of soon-to-fail components and consequently avoid any system damage or unexpected downtime. This proposal describes a course of research, which would investigate the early identification of degenerate devices (possibly prior to "wear out") by monitoring the power supply current during power-up - in essence performing health monitoring of integrated circuits in a novel and inexpensive manner. Benefits: The two commercial outcomes of this research are expected to be 1) an on-chip circuit, which can be added to any chip and 2) a stand-alone chip that can be added to any board - in both cases to monitor the health of the electronic system. Return