| Sol No.: |
Navy SBIR FY2006.2 |
| Topic No.: |
N06-164 |
| Topic Title: |
Array Clocking with Reduced Jitter Using Taped Delay Lines |
| Proposal No.: |
N062-164-0886 |
| Firm: |
FTL Systems, Inc.
1620 Greenview DR SW
Rochester, Minnesota 55902 |
| Contact: |
John Willis |
| Phone: |
(507) 288-3154 |
| Web Site: |
http://www.ftlsystems.com |
| Abstract: |
Deriving coherent antenna array clocks from a common tapped delay line driven by a synchronizing pulse per clock cycle results in reduced jitter and optimal beam forming at minimal cost. Phase one effort analytically considers both electronic and optical implementations with an option for simulation-based validation of a critical PLL circuit and other physical parameters. Analysis considers three clock configurations: 1Ghz with 100FS aperature jitter (per RFP), 21Ghz (2 times X-band) with 50FS jitter and 40GHz (2 times low end of K-band) with 10FS jitter. |
| Benefits: |
Technology resulting from this effort advances commercial capability for directional antennas, clocking in high performance parallel processors and low-jitter clock recovery for 1Ghz, 10Ghz and 40GHz serial communication protocols. To achieve maximum commercial impact, FTL's commercial interest is on the 21GHz and 40GHz (OC-768) design points above (current FTL technology adequately addresses the 1GHz configuration). In conjunction with other efforts FTL is involved with, there is a desire to extend the approach to a 100GHz clock recovery capability. |