N093-217 TITLE: Manycore, Resource Management, Dynamic/Static Application Analysis

TECHNOLOGY AREAS: Information Systems, Ground/Sea Vehicles, Electronics

ACQUISITION PROGRAM: PEO IWS 1.0

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), which controls the export and import of defense-related material and services. Offerors must disclose any proposed use of foreign nationals, their country of origin, and what tasks each would accomplish in the statement of work in accordance with section 3.5.b.(7) of the solicitation.

OBJECTIVE: Develop innovative algorithms and novel approaches that can analyze the application characteristics (static and dynamic) to configure/manage the manycore chips in a future Navy computing plant, taking into account dynamic scaling of core processing elements as the processing demand increases or decreases based on external events.

DESCRIPTION: Today, one sees multi-core packages as commodity off the self hardware providing around eight (8) cores. These current commodity solutions tend to be homogenous in nature and are supported to some extent by popular operating systems such as Microsoft and Linux with limited support from real-time OS vendors. The ability to manage each core is limited by the current core architectures and services provided by existing operating systems. Currently most resource management techniques are associated with high availability focusing on single board single core processing. The next generation resource management approaches will have to understand the complex nature of 100�s of processing elements interconnected via high speed data fabrics with applications that can span across complex memory architectures. Predictions by Intel and other semiconductor companies indicate that cores will most likely double every 18 months using 8 cores today we can produce a simple forecast that by 2012 the commercial market will see 32 cores. Today Tilera is marketing a TILE64 processor containing 64 core elements. The Navy is searching for solutions that will scale from dual core to at least 128 core elements. Any solutions should use existing standards based efforts as a starting point. Any improvements to existing standards should be brought back to the standard bodies for incorporation.

The Navy expects the next generation manycore chips will require the ability to manage resources such as: Turning on and off selected cores within a chip allowing power and energy management; adjusting voltages and frequency per core in order to boost temporary performance on a per core basis; managing the allocation of cache to individual cores either as shared or private supporting different performance needs; and managing the network that connects the numerous cores.

PHASE I: Research and investigate algorithms that can be used to allocate applications across manycore architectures. Also identify resource management services that will aid in the effective management of manycore architectures.

PHASE II: Using the research from Phase I, design and develop a model that expresses the ability to analyze application needs, allocate the application across the manycore architecture, and manage the computing plant to scale based on environmental demand.

PHASE III: Demonstrate that the algorithms can manage the complex manycore environment while achieving both resource management and desired performance. Additionally, document the design guidance that should be provided to application and infrastructure developers.

PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: The application of this technology is not limited to the DoD space and is directly applicable to various government (non defense) and private sector disciplines (e.g., IT, manufacturing, process control, finance�).

REFERENCES:
1. Thierry Collette, "Key Technologies for Many Core Architecture", CEA, LIST, www.mpsoc-forum.org/2008/slides/8-4%20Collette.pdf

2. John Sartori, and Rakesh Kumar, "Proactive Peak Power Management for Many-Core Architectures" , Coordinated Science Laboratory, http://passat.crhc.illinois.edu/rakeshk/techrep_proactive.pdf

3. "The ManyCore Shift", Microsoft Corporation, http://www.microsoft.com/presspass/events/supercomputing/docs/ManycoreWP.doc

4. Adrian Schupbach, Simon Peter, Andrew Baumann, Timothy Roscoe, System Group, Department of Computer Science, ETH Zurich, Paul Barham, Tim Harris, Revecca Isaacs, Microsoft Research, Cambridge, "Embracing diversity in the Barrelfish manycore operating system", http://people.inf.ethz.ch/troscoe/pubs/schupbach08.pdf

KEYWORDS: Multi-core. Many-Core, Resource Management, Power Management, Operating Systems, Open Architecture

** TOPIC AUTHOR (TPOC) **

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