TECHNOLOGY AREAS: Information Systems, Sensors

ACQUISITION PROGRAM: Handheld, Manpack, Small Form Fit (HMS), ACAT I, Joint Tactical Radio System

OBJECTIVE: Develop techniques and tools to optimally program a multi-core Digital Signal Processor with complex communications-related algorithms that must be shared among multiple processors. Source code may be VHDL (for FPGA devices), ANSI C, a common C++ variant, or a mixture of these. Optimization should focus on minimizing power consumption while meeting minimum performance requirements.

DESCRIPTION: Multi-core Digital Signal Processor (DSP) devices are being introduced by several firms; many of these devices contain over 100 processor cores. These multi-core devices can potentially reduce the chip count for programmable embedded applications, such as software-defined radios, and also improve capabilities and reduce power consumption and corresponding heat dissipation.

Although the device vendors provide development tools to enable programmers to port their code to these multi-core devices, the tools are not currently capable of optimizing the code � especially for processes that are shared among multiple cores. In addition, most optimization techniques focus on execution speed rather than the minimization of power consumption � which is often a more important parameter for many military and commercial applications that utilize battery power.

PHASE I: Select one or more multi-core DSP architectures (based upon available devices) and at least two complex algorithms to implement. (One algorithm should be based on C-code and the other should be a port of an algorithm native to an FPGA or other gate-based device.) Using analysis and/or Modeling and Simulation (M&S), develop and demonstrate an approach to optimizing the runtime execution of these algorithms (with minimal power consumption) across multiple processors within the device.

PHASE II: Develop a prototype tool for optimizing the development of code on a multi-core DSP device. Demonstrate the effectiveness of this tool on an actual multi-core DSP device using the algorithms of Phase I and at least two additional communications-oriented algorithms. Compare results to optimized implementations on conventional DSP and FPGA devices.

PHASE III: Complete the development of the optimization tool and refine to the degree necessary for commercialization. The product may be stand-alone or it may be integrated with a DSP vendor�s software development tools.

PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: When optimized for minimum power consumption, multi-core DSPs have a wide range of applications in consumer electronics including Smartphones, commercial radio equipment, mobile video devices, and medical equipment. There are also many military applications including mobile or unattended surveillance devices; high-speed computer processing capability in the field, and the potential of greatly increasing the targeting capabilities of weapons.

REFERENCES:
1. Asanovic, K., Bodik, R., Catanzaro, B. C., et al, "The Landscape of Parallel Computing Research: A View from Berkeley," http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183.pdf

2. Chen, L., Hu, Z., Junmin, L., and Gao, G., "Optimizing the Fast Fourier Transform on a Multi-Core Architecture," www.capsl.udel.edu/pub/doc/papers/POHLL2007-LONG.pdf

3. JTRS Open Information Repository (IR). Contains reference "waveform" source code and other documentation of interest for this project http://jtrs.calit2.net/index.php?option=com_content&task=view&id=26

KEYWORDS: multi-core; manycore; DSP; parallel; massively; JTRS