N132-145 TITLE: Advanced Radiation Hardened Data Converter Architecture

TECHNOLOGY AREAS: Information Systems, Materials/Processes, Electronics, Weapons

ACQUISITION PROGRAM: Trident II (D5), ACAT I

RESTRICTION ON PERFORMANCE BY FOREIGN CITIZENS (i.e., those holding non-U.S. Passports): This topic is "ITAR Restricted". The information and materials provided pursuant to or resulting from this topic are restricted under the International Traffic in Arms Regulations (ITAR), 22 CFR Parts 120 - 130, which control the export of defense-related material and services, including the export of sensitive technical data. Foreign Citizens may perform work under an award resulting from this topic only if they hold the "Permanent Resident Card", or are designated as "Protected Individuals" as defined by 8 U.S.C. 1324b(a)(3). If a proposal for this topic contains participation by a foreign citizen who is not in one of the above two categories, the proposal will be rejected.

OBJECTIVE: Develop an advanced radiation hardened data converter architecture which enables high speed (>25MHz) data conversion while reducing the need for multi-cycle latency and extensive active circuitry.

DESCRIPTION: Current high speed radiation hardened and commercial analog-to-digital (ADC) and digital-to-analog (DAC) converter topologies provide 1MHz to 20MHz conversion via multi-stage pipelining and error correction circuitry. This approach to data conversion results in large silicon footprints, 3 to 4 clk cycle latency, increased susceptibility to radiation effects, and increased radiation event recovery times.
This research effort seeks to develop a data conversion architecture with the following capabilities:
1. >25MHz 14 Bit data conversion
2. 1 clock cycle conversion (no latency)
3. Applicable to ADC & DAC converters
4. Reduced silicon footprint, enabling System-on-Chip (SOC) integration of multiple converters
5. Incorporation of Rad-Hard by Design (RHBD) techniques/topologies
6. Portable to existing commercial Integrated Circuit (IC) processes

PHASE I: The contractor shall deliver a detailed circuit topology with complete electrical modeling & simulation results demonstrating the capabilities of the developed architecture. Space and Strategic rad hard capabilities should be targeted. The design should target existing readily accessible IC processes. Ready to ship GDSII file should be delivered at phase end.
The contractor will propose a plan for the manufacturing and testing of prototype hardware performance in electrical and radiation environments to be conducted in Phase II.

PHASE II: The contractor shall produce prototype hardware defined in Phase I and demonstrate electrical and radiation environment performance through laboratory testing. An assessment of performance shall be delivered in formal report, along with finding and discoveries to be exploited for further advancement of the technology. The contractor will deliver updated modeling and simulation results and an updated ready to ship GDSII file at phase end.

PHASE III: Given successful completion of Phase II, a larger quantity of the integrated product shall be manufactured for larger scale testing and demonstration in candidate systems, for example Advanced IFOG or other sensor/instrument based systems.

PRIVATE SECTOR COMMERCIAL POTENTIAL/DUAL-USE APPLICATIONS: Developed circuitry could be utilized by the space industry for satellite applications. The architecture can be applied to "traditional" pipeline data converter topologies to achieve faster sampling rates and increased resolution.

REFERENCES:
1. R. Ladbury, "Radiation Hardening at the System Level," Presented at the 2007 Nuclear Science and Radiation Effects Conference Short Course, Waikiki, HI, July 2007.

2. B. D. Olson, "Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters," Ph.D. dissertation, EECS, Vanderbilt University, Nashville, TN 2010.

KEYWORDS: analog to digital converters; digital to analog converter; microelectronics; radiation-hardened-by-design; integrated circuit design; rad hard electronics

** TOPIC AUTHOR (TPOC) **

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