Multi-Instruction Set Architecture (ISA) Processing with a Peripheral Component Interconnect express (PCIe)
Navy SBIR 2019.2 - Topic N192-095
NAVSEA - Mr. Dean Putnam - [email protected]
Opens: May 31, 2019 - Closes: July 1, 2019 (8:00 PM ET)
TECHNOLOGY AREA(S): Information Systems
ACQUISITION PROGRAM: PEO IWS 1.0 AEGIS Integrated Combat System
The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 3.5 of the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.
OBJECTIVE: Develop a Peripheral Component Interconnect express (PCIe) compliant module that contains an Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) processor for Multiple Instruction Set Architecture (Multi-ISA) processing development.
DESCRIPTION: General computing components such as processors and memory exist in separate standardized groups of Instruction Set Architecture (ISA). ARM, x86, and power PC share the same interface standards (e.g., PCIe, Ethernet). However, despite evidence showing measured enhancements, the Commercial off-the-Shelf (COTS) marketplace has not provided a standard computing platform where differing ISA processors can exist as co-processors. The Office of Naval Research (ONR) has funded a basic research project called Popcorn Linux that addresses this gap in the COTS marketplace. The current implementation of Popcorn Linux requires two discrete servers of differing ISAs that connect over a common high-speed interface. However, Navy sheltered environments have limited space, weight, power, and cooling available for critical information systems infrastructure. Co-locating discrete servers with differing ISAs and connecting them with a high-speed bridge, such as PCIe or Ethernet, has many engineering and logistical complications. New technology standards, developed initially for enhancements to storage performance, capacity, and thermal profile, are applicable to implementing Multi-ISA processing within the space, weight, power, and cooling required for a single discrete server. These new specifications provide a potential
opportunity to develop a processing platform where ARM, x86-64, and any other modern ISA can be combined to enhance processing performance and reduce energy consumption. The development of a Multi-ISA processing platform will provide the Navy with the ability to deploy a highly flexible, common, secure, and upgradeable server that can scale to any mission requirement without having to use multiple systems and connections. Compared to the current state of Multi-ISA, this will save on space, weight, power, and cooling available in the sheltered infrastructure (at least 50% reduction). Such a server must have the capability to keep pace with Navy mission requirements.
Currently a Multi-ISA capable technology that is advantageous to the Navy has not developed or matured in the COTS marketplace. When considering the Navy design constraints of discrete servers, the COTS marketplace Multi-ISA technology does not meet the basic tenets of supportability, flexibility, upgradeability, and serviceability. Discrete portions of the processing industry define each processor type. Each generation of these products provide processing enhancements that benefit their standardized processing architecture. The Navy desires to develop a Multi-ISA capable platform using open standards compliant form factors.
Research on Popcorn Linux from Virginia Polytechnic Institute shows that when a single operating environment is layered across Multi-ISA devices with a high-speed interconnect (such as PCIe) results in processing efficiencies being realized [Ref. 2]. The offeror’s proposed solution must capitalize on these efficiencies to maintain an innovative processing advantage within the realm of critical information system infrastructure. The Navy desires this capability in a module-based form factor. The capability must reside on an open standards compliant x86-64 server that can accept a front accessible PCIe module defined by specifications recently released by the Enterprise and Datacenter Solid State Drive (SSD) Form Factor (EDSFF) Working Group. Relevant specifications for the server- module interface and module form factor include SFF-TA-1002, SFF-TA-1007, and SFF-TA-1009 [Refs 3-5]. The module in the offeror’s proposed solution must contain a processor that is different in ISA from the base x86-64 server. When the module is combined with a standard x86-64 server running a multi-ISA operating system, it will provide an increased processing capability (measured by a reduction in energy consumption), while limiting impact on space, weight, power, and cooling provisioned for a discrete server. Research has shown that Multi-ISA processing enhancements measured through energy consumption techniques and standard benchmark tools provide a reduction of energy consumption of approximately 10% to 30% [Ref 2]. The solution must provide a minimum of 10% energy consumption reduction. The module will connect to a discrete server using a multi-lane high-speed connector as defined in SFF-TA-1002. It will comply with the SFF-TA-1009 pin and signal specification, and maintain the physical dimensions of SFF-TA-1007 with the exception of overall module thickness. Overall module thickness shall not exceed a 36mm thick form factor with a maximum sustained power rating of up to 80W. The offeror is encouraged to use more than one connector due to the power requirements of a standard processor.
However, the offeror must limit overall module thickness based on the number of connectors used. The energy consumption techniques and performance benchmarks described in Virginia Tech’s Popcorn Linux research papers will be the standard method used to evaluate the viability of any proposed solution.
PHASE I: Provide a concept for a PCIe module containing a processor with a differing ISA from the server and a server capable of executing a Multi-ISA operating system. Demonstrate that the concept shows it can feasibly meet the requirements of the Description. Establish feasibility with conceptual models and drawings. Develop a Phase II plan. The Phase I Option, if exercised, will include the initial design specifications and capabilities description to build a prototype solution in Phase II.
PHASE II: Develop and deliver a prototype PCIe module containing a processor and x86-64 server that conform to the specifications in the Description. Ensure that the prototype demonstrates Multi-ISA capabilities by running a Multi-ISA capable operating system, such as Popcorn Linux version 3.2.
PHASE III DUAL USE APPLICATIONS: Support the Navy in transitioning the technology to Navy use. Integrate the final product into a discrete server provided by the Government. Support initial integration testing of the ARM processor module. Perform non-destructive environmental qualification testing on the module and server applicable to Navy sheltered environment requirements. A Navy technical authority and the AEGIS Integrated Combat System (ICS) Program Office will give consideration for the processor module to be part of future designs within critical information technology infrastructure.
This technology can be used in crypto currency mining, high-performance gaming machines, and microprocessor firmware development. When the form factor is maintained, but the processor is replaced with an Application- specific Integrated Circuit (ASIC) or Field-programmable Gate Array (FPGA) additional use cases ranging from cybersecurity-related applications to line-rate image processing can be realized. In general, this technology is applicable in any Information Technology or Operational Technology use case where higher processing performance and lower energy consumption is desired.
1. Tallis, Billy and Shilov, Anton. “Intel Introduces “Ruler” Server SSD Form-Factor: SFF-TA-1002 Connector, PCIe Gen 5 Ready.” AnandTech, 09 August 2017. https://www.anandtech.com/show/11702/intel-introduces-new- ruler-ssd-for-servers
2. Barbalace, Antonio, Lyerly, Robert, Jelesnianski, Christopher, Carno, Anthony, Chuang, Ho-Ren, Legout, Vincent and Ravindran, Binoy. “Breaking the Boundaries in Heterogeneous-ISA Datacenters.” Bradley Department of Electrical and Computer Engineering, Virginia Tech, , 19 April 2017. http://popcornlinux.org/images/publications/asplos2017.pdf
3. Norton, John. “Specification for Protocol Agnostic Multi-Lane High Speed Connector.” SFF-TA-1002 Rev 1.1, January 18, 2018. http://www.sina.org/sff/specifications
4. Constantine, Anthony. "Enterprise and Datacenter 1U Long SSD Form Factor.” SFF-TA-1007 Rev 1.0.0, February 7, 2018. http://www.sina.org/sff/specifications
5. Constantine, Anthony. "Enterprise and Datacenter SSD Pin and Signal Specification.” SFF-TA-1009 Rev 1.0, March 23, 2018. http://www.snia.org/sff/specifications
KEYWORDS: Popcorn Linux; ARM; x86-64; Heterogeneous-ISA; Multi-ISA; EDSFF; Instruction Set Architecture