N232-113 TITLE: On-Chip Optical Isolation for Integrated Photonics
OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics;Nuclear;Quantum Science
The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.
OBJECTIVE: Develop on-chip optical isolators at telecom wavelengths with a high isolation ratio, wide bandwidth, and low insertion loss.
DESCRIPTION: A complete integrated photonics toolset requires optical isolators and circulators. These components improve the routing of optical power on chip by blocking light from entering chosen ports [Refs 1,2]. Such a component is crucial to the performance of on-chip lasers. While in-line fiber-optic versions of these components are available, on-chip integration has been a major challenge.
Optical isolators and circulators rely on the breaking of Lorentz reciprocity. This can only be achieved using one of three approaches: nonlinear effects, magneto-optical effects, and spatio-temporal modulation [Ref 3].
In the past two years on-chip optical isolation in the C-band has been demonstrated for the first time in two separate approaches. First, advances in the deposition of cerium-doped yttrium iron garnet (Ce:YIG), a magneto-optical material, have allowed for the integration of thin-films onto the sidewalls of both silicon (Si) and silicon nitride (Si3N4) waveguides. Optical isolation in both transverse electric (TE) and transverse magnetic (TM) polarizations has been demonstrated in these platforms [Ref 5]. Second, two separate groups simultaneously demonstrated optical isolation with spatio-temporal modulation of piezoelectric modulators integrated on waveguides [Refs 3,4].
SSP calls for the development of an on-chip optical isolation capability at telecom wavelengths. Among other capabilities, this technology will enable integration of sensitive optical sources on photonic integrated circuits. Both spatio-temporal and magneto-optic solutions are encouraged to respond to this SBIR topic. As the technology is matured, performers will collaborate with SSP and government contractors to integrate the technology into relevant platforms. This collaboration will also seek to develop a technology transfer plan for commercial-scale photonics foundry fabrication.
PHASE I: Perform a design and fabrication analysis to assess the feasibility of the proposed technique or material development for on-chip isolation in the telecom wavelength range for use in integrated photonic devices. Include the expected isolation ratio (ideally > 30 dB) for the technique, expected die area required, insertion loss introduced (< 3 dB insertion loss preferred), and bandwidth. Identify risks and risk mitigation strategies. The Phase I Option, if exercised, will include the initial design specifications and capabilities description to build prototype solutions in Phase II.
PHASE II: Fabricate and characterize five (5) prototypes that demonstrate the on-chip isolation capability. Variability of key metrics (isolation ratio, bandwidth) < 3% and optical insertion loss < 3 dB should be addressed with a mitigation plan to enable highly reliable performance as the system matures.
The final report will include a discussion of potential near-term and long-term development efforts that would improve the technology�s performance and ease of fabrication. It will also include an evaluation of the cost of fabrication and how that might be reduced in the future. The prototypes should be delivered by the end of Phase II.
PHASE III DUAL USE APPLICATIONS: Based on the prototypes and continual advancement of photonics capabilities, on-chip isolation technology should lead to dramatic improvements in the feasibility of achieving fully integrated photonic devices. Support the Navy in transitioning the technology to Navy use. The prototypes will be evaluated through optical characterization and testing with relevant adjacent devices. The end product technology could be leveraged to bring photonic imaging and sensing towards a more mature state with a lower size, weight, and power (SWaP) profile that could make it more attractive for optical communication and Light Detecting and Ranging (LIDAR) as well as in the biomedical, navigation, and vehicle autonomy markets.
KEYWORDS: Photonic integrated circuits; optical; isolation; magneto-optics; spatio-temporal; telecom; photonics
** TOPIC NOTICE **
The Navy Topic above is an "unofficial" copy from the Navy Topics in the DoD 23.2 SBIR BAA. Please see the official DoD Topic website at www.defensesbirsttr.mil/SBIR-STTR/Opportunities/#announcements for any updates.
The DoD issued its Navy 23.2 SBIR Topics pre-release on April 19, 2023 which opens to receive proposals on May 17, 2023, and closes June 14, 2023 (12:00pm ET).
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|5/1/23||Q.||1. Does it require that on-chip oscillators only for CW light? or pulsed sources as well?
2.The solicitation mentions that the on-chip isolators will be integrated into relevant platforms. What platform is it? This will influence the isolator design. Do we need to prove the on-chip isolator can be fabricated on the same chip without affecting other components?
3.For the spatio-temporal modulation method, any requirement on the driving power?
|A.||1. On-chip isolation is of interest for a wide range of applications involving both CW and pulsed light. Optical pulse isolation efficacy is related to optical bandwidth. Interested in solutions that maximize bandwidth and isolation ratio while minimizing insertion loss.
2. The technology is of interest for a variety of platforms such as those identified in the Phase III dual use application section of the topic solicitation. Any solutions that address the stated goals and are compatible with on-chip integration are of interest, will be considered and evaluated.
3. There is no drive power requirement, although a path to low-power operation is highly desired.