N232-116 TITLE: Direct Etched Silicon Wafer Bonding for Micro-Electromechanical Systems (MEMS).
OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics;Nuclear;Space Technology
The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.
OBJECTIVE: Develop a reliable direct silicon wafer bonding process with etched wafers.
DESCRIPTION: Direct silicon wafer bonding is the process of adhering two wafers together without any intermediate layers. Although this process is employed currently, it necessitates high standards in both surface geometry and roughness. Etched silicon wafers are often not considered for direct wafer bonding because of those standards. Adhesion layers, such as a eutectic metal layer, may overcome the stringent geometry standards required for direct bonding, but the mismatches of coefficient of thermal expansion (CTE) between the adhesion layer and the silicon device may lead to performance impacts for high stability sensors, such as long-term creep. Examples of existing research for direct wafer bonding can be found in the referenced articles [Refs 1-4].
MEMS sensors are more frequently being considered as alternatives to conventionally machined sensors in order to meet performance requirements in a low size, weight, and power (SWaP) package. This process is likely to bring value to multiple industries as the need for stability and reliability become more important.
PHASE I: Design a direct wafer bonding process with the desired goals of 1) forming a complete bond with at least one etched silicon wafer (bond areas no less than 100 �m x 100 �m, etch depth no greater than 200 �m); 2) demonstrating a hermetic seal with both an inert gas (such as dry nitrogen) or vacuum after dicing into separate devices; 3) ensuring reliability of the bond through thermal environments (between -55�C to 85�C) and mechanical environments such as vibration, shock, bond strength, and constant acceleration (see MIL-STD-883-2 for reference). The Phase I study shall assess all aspects of the bonding process and justify the feasibility and practicality of the designed approach. The Phase I Option, if exercised, will include the initial design specifications and capabilities to build a prototype solution in Phase II.
PHASE II: Based on the Phase I design and execution plan, fabricate and characterize a small lot (up to Qty: 5 wafers) of silicon articles. This characterization may include hermetic leak checking, bond strength tests, and wafer uniformity for sample MEMS devices. Wafers will need to be etched, bonded, and diced to resemble a typical MEMS device process. The prototypes, test samples, and characterization results should be delivered by the end of Phase II.
PHASE III DUAL USE APPLICATIONS: Based on the prototypes developed in Phase II, continuing development must lead to productization of the direct wafer bonding process. Qualify this product by inserting and demonstrating the bonding process into a known microfabrication process for a MEMS design. If required, subject the devices incorporating the wafer bonding process to several common test environments, including radiation and vibration environments.
While this technology is aimed at multiple national interest applications, wafer bonding is used more broadly in the MEMS industry. A direct bonding process for etched wafers is likely to bring value to existing commercial applications such as space and autonomous vehicle navigation to improve both the reliability and performance of high-end MEMS sensors.
KEYWORDS: Direct wafer bonding; MEMS; micro-electromechanical; systems; microfabrication; wafers
** TOPIC NOTICE **
The Navy Topic above is an "unofficial" copy from the Navy Topics in the DoD 23.2 SBIR BAA. Please see the official DoD Topic website at www.defensesbirsttr.mil/SBIR-STTR/Opportunities/#announcements for any updates.
The DoD issued its Navy 23.2 SBIR Topics pre-release on April 19, 2023 which opens to receive proposals on May 17, 2023, and closes June 14, 2023 (12:00pm ET).
Direct Contact with Topic Authors: During the pre-release period (April 19, 2023 through May 16, 2023) proposing firms have an opportunity to directly contact the Technical Point of Contact (TPOC) to ask technical questions about the specific BAA topic. Once DoD begins accepting proposals on May 17, 2023 no further direct contact between proposers and topic authors is allowed unless the Topic Author is responding to a question submitted during the Pre-release period.
SITIS Q&A System: After the pre-release period, until May 31, (at 12:00 PM ET), proposers may submit written questions through SITIS (SBIR/STTR Interactive Topic Information System) at www.dodsbirsttr.mil/topics-app/ by logging in and following instructions. In SITIS, the questioner and respondent remain anonymous but all questions and answers are posted for general viewing.
Topics Search Engine: Visit the DoD Topic Search Tool at www.dodsbirsttr.mil/topics-app/ to find topics by keyword across all DoD Components participating in this BAA.
|5/24/23||Q.||Would it be possible to get clarification on the deliverables for Phase I that would convey feasibility to permit advancing to Phase II?
"The Phase I study shall assess all aspects of the bonding process and justify the feasibility and practicality of the designed approach." Is it the Navy's intention to have process designed or a demonstration of the bond? Demonstration of hermitic sealing, vibration, thermal, etc test during the Phase I Base?
|A.||Firm's innovation and approach within the requirements and feasibility at the end of Phase I, will determine potential advancement to Phase II.
The intent of Phase I is to have a process designed and specified. Modeling and calculations should show that the designed process should be reliable through the environments. Prototypes will be fabricated as part of Phase II.
|5/19/23||Q.||1. Surface roughness can vary quite a bit based on manufacturing conditions (e.g. thickness, origination, time, etc.) Do you have an estimate on surface roughness to expect?
2. For hermetic sealing demonstration, is there a specific design you would like to see?
3. For Phase I, should the hermetically sealed devices be diced after they are bonded? Is the purpose to show the bonds survive the dicing process or to show scalability�both?
4. Solicitation states etch depth no greater than 200�m; what is the origin of this metric?
|A.||1. A maximum surface roughness could be specified for the bonding conditions. Processes of interest that could affect surface roughness include lithography, DRIE, oxidation, and polysilicon deposition.
2. There is no specific design at this time.
3. The hermetically-sealed devices is recommended to be diced after bonding � for both scalability and survivability.
4. Some devices under consideration may be etched to that depth.
|5/17/23||Q.||1. Can you specify the type of MEMS devices this will be applied towards?
2. What is the thermochemical profile of the intended MEMS process that the wafer bonding process will have to be compatible with?
3. To clarify, if the above details cannot be shared at this time, design and testing of the wafer bonding process with an etched wafer and blank wafer is acceptable, correct?
4. What is the desired wafer diameter?
5. A minimum bond area and minimum etch depth is specified, is there a maximum and minimum respectively?
|A.||1. This technique should be applicable to many types of high-precision sensors that use wafer-level seals, such as those identified in the Phase III Dual-Use Application section.
2. The bond may be completed as the last step if needed � thus no further thermochemical processes.
3. Yes, that is the intent.
4. 150 mm wafers are appropriate.
5. There is currently at this time no defined minimum bond area and/or minimum etch depth specified.
|5/17/23||Q.||Is there a maximum temperature or thermal budget (during bonding or after bonding)?|
|A.||The max temperature of the bonding process is recommended to be at or below 350 C. Bonding may be done as the final step, so an after-bonding max temperature could be within the stated operating range.|