N23B-T034 TITLE: Silicon Photonics Integration
OUSD (R&E) CRITICAL TECHNOLOGY AREA(S): Microelectronics
OBJECTIVE: Develop new methodologies (or improve existing methodologies) to determine the reliability of silicon Photonic Integrated Circuit (PIC) devices and identify failure mechanisms with an emphasis on determining the influence of neighboring intra-chip devices, input/output components, and packaging.
DESCRIPTION: PICs provide a tremendous opportunity to significantly improve the performance of future generation microelectronic systems. PICs of continuously increasing complexity are finding applications in analog signal processing, optical communication, light detection and ranging (lidar), chemical and biological sensing, artificial intelligence (AI), quantum applications, and custom Department of Defense (DoD) applications. For example, PICs are a key part of high-capacity transceivers and switches for internet data centers, and are under investigation for transmitters and receivers for free space optical communications, hyperspectral imaging devices, light sources for medical diagnostic equipment, and light sources for atomic clocks and gyroscopes. The reliability of PIC devices applicable to DoD avionics, sensors, and electronic warfare (EW) continues to be under study by the DoD Science & Technology community. Verification and validation of integrated photonic device reliability is paramount to opening the door for technology transition opportunity discussions with programs. Laboratory testing of state-of-the-art silicon photonic devices under development in the DoD or in commercial-sector production requires integration with electrical and optical input/output devices at the package level.
Military uses of PICs require environmental ruggedness and reliable operation on the order of 100,000 hr mean time or longer between failures. Device operation has to be sustained under extreme conditions, such as high temperature (> 100 �C), low temperature (< -40 �C), high radiation, vibration, shock, and humidity. This SBIR topic seeks to evaluation of the underlying reliability physics of silicon based PIC chips and their corresponding packages, to improve the understanding of their failure mechanisms. Representative silicon-based PICs should be selected, and the main degradation modes should be experimentally and theoretically evaluated. Possible degradation modes include semiconductor crystal point defects and dislocations, dielectric and semiconductor optical absorption changes, material transition interface damage and passivation, dopant diffusion, material mechanical stress, metal diffusion, outgassing, solder creep, and intermetallic compound instability. At the package level possible degradation modes include optical coupling efficiency degradation at optical waveguide and/or fiber optic interfaces, electrical bond (bump or wire) failure, and loss of hermetic seal. These representative PICs should be subjected to Highly Accelerated Life Test (HALT) experiments to uncover failures, which will then improve the understanding of device failure physics and packaging failures after appropriate analysis. Individual chips, chip-on-carrier (CoC), and fully packaged devices should be considered for HALT plan creation and evaluation. Acceleration factors such as temperature, electrical bias, optical power, radiation and mechanical stress should be considered according to MIL-HDBK 217 and MIL-STD-810. Particular emphasis should be placed on understanding the influence of individual PIC devices on the reliability of the optical coupling and packaging. PIC integration with planar lightwave circuits (PLCs) and other optical waveguide devices should also be investigated.
Possible failure mechanism evaluation tools to be used include X-Ray radiography, Scanning Electron Microscope (SEM), Transmission Electron Microscope (TEM), Optical beam induced current (OBIC), Focused Ion Beam Etching (FIB), Deep-level Transient Spectroscopy (DLTS), and Atomic Force Microscope (AFM) among many others.
The models verified through experimental testing and the improved understanding of PIC/PLC device and package reliability physics will be used to create reliability prediction models and software for PICs/PLCs planned for use in military environments. Due to the large variety of PIC/PLC architectures and base materials, both in fabrication and under development, it is possible that several methods will be identified to extrapolate the PIC lifetime depending on the device specifics.
PHASE I: Define innovative methods to model, and predict silicon PIC and packaged silicon PIC reliability, including experimental test plans based on state-of-the-art reliability physics of failure and modeling, and simulation analyses to ascertain existing software prediction shortcomings. Develop models and experimental test plans for application to silicon-photonic integrated circuit devices, including circuit layouts and packages designed to accommodate these test plans. The focus should be on PIC circuits and components relevant to microwave and analog signal processing. Phase I effort will include prototype plans to be developed under Phase II.
PHASE II: Acquire representative silicon PIC and packaged silicon PIC devices for experimental testing and perform testing. Develop, demonstrate, and validate the reliability prediction models. Subject silicon PIC and packaged silicon PIC devices to environmental and mechanical test stresses based on modeling and simulation results, reliability engineering principles, and experimental test plans. Perform root cause analyses of device failures to understand silicon PIC, optical input/output, electrical input/output device, and package interactions and reliability prediction interdependencies. Develop, demonstrate, and deliver a packaged silicon PIC reliability software package for subsequent independent verification and validation.
PHASE III DUAL USE APPLICATIONS: Transition the software package to enable DoD and silicon photonic device producers to predict reliability. Commercial data centers or internet facilities are commercial sector applications of silicon photonics.
KEYWORDS: Silicon photonics; reliability; failure analysis; modeling; simulation tools; packaging
** TOPIC NOTICE **
The Navy Topic above is an "unofficial" copy from the Navy Topics in the DoD 23.B STTR BAA. Please see the official DoD Topic website at www.defensesbirsttr.mil/SBIR-STTR/Opportunities/#announcements for any updates.
The DoD issued its Navy 23.B STTR Topics pre-release on April 19, 2023 which opens to receive proposals on May 17, 2023, and closes June 14, 2023 (12:00pm ET).
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